113 lines
2.7 KiB
Markdown
113 lines
2.7 KiB
Markdown
# Memory
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## Default Memory Access Permissions
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The Cortex-M3 memory map has a default configuration for memory access permissions
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Default memory access permission is used when either:
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* No MPU is present
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* MPU is present but disabled
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Otherwise MPU will determine
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When a memory access is blocked the fault exception takes place immediately.
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```python { cmd matplotlib hide }
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import pymupdf
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from PIL import Image
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doc = pymupdf.open("./pdf/L4.pdf")
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pix = doc[12].get_pixmap()
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img = Image.frombytes("RGB", [pix.width, pix.height], pix.samples)
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plt.axis('off')
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plt.subplots_adjust(left=0, right=1, top=1, bottom=0)
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plt.imshow(img)
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plt.show()
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```
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## MPU(Memory Protection Unit)
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MPU
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Regions can be overlapped only in ARMv7
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## Bit-Band Operations
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it allows a single load/store opertation to access a **single data bit**.
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Bit-band regions:
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* The first 1MB of the SRAM region
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* The first 1MB of theperipheral region
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They can be accessed via a separate memory region called the bit-band alias.
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Bit-Banding done transparently by **bus matrix**.
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### Write to Bit-Band Alias
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* Without Bit-Band:
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```armasm
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LDR R0, =0x20000000 ; Setup address
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LDR R1, [R0] ; Read
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ORR.W R1, #0x4 ; Modify bit
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STR R1, [R0] ; Write back result
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```
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* With Bit-Band:
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```armasm
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LDR R0, =0x22000008 ; Setup address
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MOV R1, #1 ; Setup data
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STR R1, [R0] ; Write
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```
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### Read from the Bit-Band Alias
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To get bit 2 in word data in address `0x20000000`:
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* Without
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```armasm
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LDR R0, =0x20000000 ; Setup address
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LDR R1, [R0] ; Read
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UBFX.W R1, R1, #2, #1 ; Extract Bit[2]
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```
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* With
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```armasm
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LDR R0, = 0x22000008 ; Setup address
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LDR R1, [R0] ; Read
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```
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### Advantages of using bit-band ops
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* Faster bit operations with fewer instructions
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* Prevent a **race condition** problem in bit modification
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### Usecase in C
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* There is no native support of bit-band ops in most C compilers
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* The simplest solution is to separately declare the address and the bit-band alias of a memory location
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```c
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#define DEVICE_REGO *((volatile unsigned long *) 0x40000000)
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#define DEVICE REGO_BIT0 *((volatile unsigned long *) 0x42000000)
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#define DEVICE REGO_BIT1 *((volatile unsigned long *) 0x42000004)
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```
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## Unaligned Transfers
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Coretex-M3 optionally supports unaligned transfers on single accesses.
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Data memory accesses can be defined as aligned or unaligned.
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Unaligned transfers are converted into multiple aligned transfers by the processor's bus interface unit:
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* transparent to application programmers
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* it takes more clock cycles for a single data access
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Limitations:
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* Not supported in load/store multiple instructions
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* Stack operations (PUSH/POP) must be aligned
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* Exclusive access must be aligned
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* Unaligned transfers are not supported in bit-band ops |