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Author SHA1 Message Date
yenru0
40efcbb1ad add lab w8 (week 9) 2025-11-12 15:02:49 +09:00
yenru0
c6dff74333 add P7 P8 pdf 2025-11-12 15:02:26 +09:00
13 changed files with 1576 additions and 0 deletions
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labs/lab_w8/.ccsproject Normal file
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labs/lab_w8/.cproject Normal file
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169
labs/lab_w8/Clock.c Normal file
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// Clock.c
// Runs on the MSP432
// Daniel and Jonathan Valvano
// February 23, 2017
/* This example accompanies the book
"Embedded Systems: Introduction to Robotics,
Jonathan W. Valvano, ISBN: 9781074544300, copyright (c) 2019
For more information about my classes, my research, and my books, see
http://users.ece.utexas.edu/~valvano/
Simplified BSD License (FreeBSD License)
Copyright (c) 2019, Jonathan Valvano, All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are
those of the authors and should not be interpreted as representing official
policies, either expressed or implied, of the FreeBSD Project.
*/
#include <stdint.h>
#include "msp.h"
uint32_t ClockFrequency = 3000000; // cycles/second
//static uint32_t SubsystemFrequency = 3000000; // cycles/second
// ------------Clock_InitFastest------------
// Configure the system clock to run at the fastest
// and most accurate settings. For example, if the
// LaunchPad has a crystal, it should be used here.
// Call BSP_Clock_GetFreq() to get the current system
// clock frequency for the LaunchPad.
// Input: none
// Output: none
uint32_t Prewait = 0; // loops between BSP_Clock_InitFastest() called and PCM idle (expect 0)
uint32_t CPMwait = 0; // loops between Power Active Mode Request and Current Power Mode matching requested mode (expect small)
uint32_t Postwait = 0; // loops between Current Power Mode matching requested mode and PCM module idle (expect about 0)
uint32_t IFlags = 0; // non-zero if transition is invalid
uint32_t Crystalstable = 0; // loops before the crystal stabilizes (expect small)
void Clock_Init48MHz(void){
// wait for the PCMCTL0 and Clock System to be write-able by waiting for Power Control Manager to be idle
while(PCM->CTL1&0x00000100){
// while(PCMCTL1&0x00000100){
Prewait = Prewait + 1;
if(Prewait >= 100000){
return; // time out error
}
}
// request power active mode LDO VCORE1 to support the 48 MHz frequency
PCM->CTL0 = (PCM->CTL0&~0xFFFF000F) | // clear PCMKEY bit field and AMR bit field
// PCMCTL0 = (PCMCTL0&~0xFFFF000F) | // clear PCMKEY bit field and AMR bit field
0x695A0000 | // write the proper PCM key to unlock write access
0x00000001; // request power active mode LDO VCORE1
// check if the transition is invalid (see Figure 7-3 on p344 of datasheet)
if(PCM->IFG&0x00000004){
IFlags = PCM->IFG; // bit 2 set on active mode transition invalid; bits 1-0 are for LPM-related errors; bit 6 is for DC-DC-related error
PCM->CLRIFG = 0x00000004; // clear the transition invalid flag
// to do: look at CPM bit field in PCMCTL0, figure out what mode you're in, and step through the chart to transition to the mode you want
// or be lazy and do nothing; this should work out of reset at least, but it WILL NOT work if Clock_Int32kHz() or Clock_InitLowPower() has been called
return;
}
// wait for the CPM (Current Power Mode) bit field to reflect a change to active mode LDO VCORE1
while((PCM->CTL0&0x00003F00) != 0x00000100){
CPMwait = CPMwait + 1;
if(CPMwait >= 500000){
return; // time out error
}
}
// wait for the PCMCTL0 and Clock System to be write-able by waiting for Power Control Manager to be idle
while(PCM->CTL1&0x00000100){
Postwait = Postwait + 1;
if(Postwait >= 100000){
return; // time out error
}
}
// initialize PJ.3 and PJ.2 and make them HFXT (PJ.3 built-in 48 MHz crystal out; PJ.2 built-in 48 MHz crystal in)
PJ->SEL0 |= 0x0C;
PJ->SEL1 &= ~0x0C; // configure built-in 48 MHz crystal for HFXT operation
// PJDIR |= 0x08; // make PJ.3 HFXTOUT (unnecessary)
// PJDIR &= ~0x04; // make PJ.2 HFXTIN (unnecessary)
CS->KEY = 0x695A; // unlock CS module for register access
CS->CTL2 = (CS->CTL2&~0x00700000) | // clear HFXTFREQ bit field
0x00600000 | // configure for 48 MHz external crystal
0x00010000 | // HFXT oscillator drive selection for crystals >4 MHz
0x01000000; // enable HFXT
CS->CTL2 &= ~0x02000000; // disable high-frequency crystal bypass
// wait for the HFXT clock to stabilize
while(CS->IFG&0x00000002){
CS->CLRIFG = 0x00000002; // clear the HFXT oscillator interrupt flag
Crystalstable = Crystalstable + 1;
if(Crystalstable > 100000){
return; // time out error
}
}
// configure for 2 wait states (minimum for 48 MHz operation) for flash Bank 0
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL&~0x0000F000)|FLCTL_BANK0_RDCTL_WAIT_2;
// configure for 2 wait states (minimum for 48 MHz operation) for flash Bank 1
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL&~0x0000F000)|FLCTL_BANK1_RDCTL_WAIT_2;
CS->CTL1 = 0x20000000 | // configure for SMCLK divider /4
0x00100000 | // configure for HSMCLK divider /2
0x00000200 | // configure for ACLK sourced from REFOCLK
0x00000050 | // configure for SMCLK and HSMCLK sourced from HFXTCLK
0x00000005; // configure for MCLK sourced from HFXTCLK
CS->KEY = 0; // lock CS module from unintended access
ClockFrequency = 48000000;
// SubsystemFrequency = 12000000;
}
// ------------Clock_GetFreq------------
// Return the current system clock frequency for the
// LaunchPad.
// Input: none
// Output: system clock frequency in cycles/second
uint32_t Clock_GetFreq(void){
return ClockFrequency;
}
// delay function
// which delays about 6*ulCount cycles
// ulCount=8000 => 1ms = (8000 loops)*(6 cycles/loop)*(20.83 ns/cycle)
//Code Composer Studio Code
void delay(unsigned long ulCount){
__asm ( "pdloop: subs r0, #1\n"
" bne pdloop\n");
}
// ------------Clock_Delay1us------------
// Simple delay function which delays about n microseconds.
// Inputs: n, number of us to wait
// Outputs: none
void Clock_Delay1us(uint32_t n){
n = (382*n)/100;; // 1 us, tuned at 48 MHz
while(n){
n--;
}
}
// ------------Clock_Delay1ms------------
// Simple delay function which delays about n milliseconds.
// Inputs: n, number of msec to wait
// Outputs: none
void Clock_Delay1ms(uint32_t n){
while(n){
delay(ClockFrequency/9162); // 1 msec, tuned at 48 MHz
n--;
}
}

99
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/**
* @file Clock.h
* @brief Provide functions that initialize the MSP432 clock module
* @details Reconfigure MSP432 to run at 48 MHz
* @version TI-RSLK MAX v1.1
* @author Daniel Valvano and Jonathan Valvano
* @copyright Copyright 2019 by Jonathan W. Valvano, valvano@mail.utexas.edu,
* @warning AS-IS
* @note For more information see http://users.ece.utexas.edu/~valvano/
* @date June 28, 2019
******************************************************************************/
/* This example accompanies the book
"Embedded Systems: Introduction to Robotics,
Jonathan W. Valvano, ISBN: 9781074544300, copyright (c) 2019
For more information about my classes, my research, and my books, see
http://users.ece.utexas.edu/~valvano/
Simplified BSD License (FreeBSD License)
Copyright (c) 2017, Jonathan Valvano, All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are
those of the authors and should not be interpreted as representing official
policies, either expressed or implied, of the FreeBSD Project.
*/
#include <stdint.h>
/**
* Configure the MSP432 clock to run at 48 MHz
* @param none
* @return none
* @note Since the crystal is used, the bus clock will be very accurate
* @see Clock_GetFreq()
* @brief Initialize clock to 48 MHz
*/
void Clock_Init48MHz(void);
/**
* Return the current bus clock frequency
* @param none
* @return frequency of the system clock in Hz
* @note In this module, the return result will be 3000000 or 48000000
* @see Clock_Init48MHz()
* @brief Returns current clock bus frequency in Hz
*/
uint32_t Clock_GetFreq(void);
/**
* Simple delay function which delays about n milliseconds.
* It is implemented with a nested for-loop and is very approximate.
* @param n is the number of msec to wait
* @return none
* @note This function assumes a 48 MHz clock.
* This implementation is not very accurate.
* To improve accuracy, you could tune this function
* by adjusting the constant within the implementation
* found in the <b>Clock.c</b> file.
* For a more accurate time delay, you could use the SysTick module.
* @brief Software implementation of a busy-wait delay
*/
void Clock_Delay1ms(uint32_t n);
/**
* Simple delay function which delays about n microseconds.
* It is implemented with a nested for-loop and is very approximate.
* @param n is the number of usec to wait
* @return none
* @note This function assumes a 48 MHz clock.
* This implementation is not very accurate.
* To improve accuracy, you could tune this function
* by adjusting the constant within the implementation
* found in the <b>Clock.c</b> file.
* For a more accurate time delay, you could use the SysTick module.
* @brief Software implementation of a busy-wait delay
*/
void Clock_Delay1us(uint32_t n);

296
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#include "Clock.h"
#include "msp.h"
#include <stdint.h>
//=============================================================================
// 1. 상수 정의 (Constants)
//=============================================================================
// (!!주의!!) SMCLK = 12MHz 기준입니다.
#define RPM_MAGIC_NUMBER 2000000
#define TIMER_A0_PWM_PERIOD_TICKS 15000
#define STALL_TIMER_PERIOD 50000
#define LEFT_PWM_PIN BIT7
#define LEFT_DIR_PIN BIT5
#define LEFT_SLEEP_PIN BIT7
#define RIGHT_PWM_PIN BIT6
#define RIGHT_DIR_PIN BIT4
#define RIGHT_SLEEP_PIN BIT6
#define TURN_30_DEG_PULSES 60
#define TURN_SPEED 2000
static volatile uint32_t g_left_pulse_period = 0;
static volatile uint32_t g_right_pulse_period = 0;
static volatile uint16_t g_last_left_capture = 0;
static volatile uint16_t g_last_right_capture = 0;
static volatile uint32_t g_left_pulse_count = 0;
static volatile uint32_t g_right_pulse_count = 0;
static volatile uint8_t g_left_new_data = 0;
static volatile uint8_t g_right_new_data = 0;
/*
FUNCTION DECLARATIONS
*/
void Motor_Init(void);
void Motor_Left_Forward(uint16_t speed);
void Motor_Left_Backward(uint16_t speed);
void Motor_Right_Forward(uint16_t speed);
void Motor_Right_Backward(uint16_t speed);
void Motor_Left_Stop(void);
void Motor_Right_Stop(void);
void Motor_Stop_All(void);
void rpm_tachometer_init(void);
uint32_t get_left_rpm(void);
uint32_t get_right_rpm(void);
void reset_pulse_counts(void);
uint32_t get_left_pulse_count(void);
uint32_t get_right_pulse_count(void);
static void capture_init_timer_A3(void);
static void Timer_A2_Stall_Init(void);
void Rotate_30_Degrees(void);
/*
MAIN FUNCTION
*/
int main(void) {
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD;
Clock_Init48MHz();
Motor_Init();
rpm_tachometer_init();
__enable_irq();
__delay_cycles(12000000);
Rotate_30_Degrees();
while (1) {
Clock_Delay1ms(1000);
}
}
/*
IMPLEMENTATIONS 30DEG ROT. FUNCTION
*/
void Rotate_30_Degrees(void) {
reset_pulse_counts();
Motor_Left_Forward(TURN_SPEED);
Motor_Right_Backward(TURN_SPEED);
uint8_t left_reached = 0;
uint8_t right_reached = 0;
while (left_reached == 0 || right_reached == 0) {
if (left_reached == 0) {
if (get_left_pulse_count() >= TURN_30_DEG_PULSES) {
Motor_Left_Stop();
left_reached = 1;
}
}
if (right_reached == 0) {
if (get_right_pulse_count() >= TURN_30_DEG_PULSES) {
Motor_Right_Stop();
right_reached = 1;
}
}
__delay_cycles(1000);
}
Motor_Stop_All();
}
/*
IMPLEMENTATION MOTOR RELATIVE FUNCTIONS
*/
void Motor_Init(void) {
P3->OUT |= (LEFT_SLEEP_PIN | RIGHT_SLEEP_PIN);
P3->DIR |= (LEFT_SLEEP_PIN | RIGHT_SLEEP_PIN);
P3->SEL0 &= ~(LEFT_SLEEP_PIN | RIGHT_SLEEP_PIN);
P3->SEL1 &= ~(LEFT_SLEEP_PIN | RIGHT_SLEEP_PIN);
P5->OUT &= ~(LEFT_DIR_PIN | RIGHT_DIR_PIN);
P5->DIR |= (LEFT_DIR_PIN | RIGHT_DIR_PIN);
P5->SEL0 &= ~(LEFT_DIR_PIN | RIGHT_DIR_PIN);
P5->SEL1 &= ~(LEFT_DIR_PIN | RIGHT_DIR_PIN);
P2->OUT &= ~(LEFT_PWM_PIN | RIGHT_PWM_PIN);
P2->DIR |= (LEFT_PWM_PIN | RIGHT_PWM_PIN);
P2->SEL0 |= (LEFT_PWM_PIN | RIGHT_PWM_PIN);
P2->SEL1 &= ~(LEFT_PWM_PIN | RIGHT_PWM_PIN);
TIMER_A0->CTL = TIMER_A_CTL_SSEL__SMCLK |
TIMER_A_CTL_ID__1 |
TIMER_A_CTL_CLR;
TIMER_A0->CCR[0] = TIMER_A0_PWM_PERIOD_TICKS;
TIMER_A0->CCTL[3] = TIMER_A_CCTLN_OUTMOD_7;
TIMER_A0->CCR[3] = 0;
TIMER_A0->CCTL[4] = TIMER_A_CCTLN_OUTMOD_7;
TIMER_A0->CCR[4] = 0;
TIMER_A0->CTL |= TIMER_A_CTL_MC__UP;
}
void Motor_Left_Forward(uint16_t speed) {
if (speed > TIMER_A0_PWM_PERIOD_TICKS) speed = TIMER_A0_PWM_PERIOD_TICKS;
P5->OUT &= ~LEFT_DIR_PIN;
TIMER_A0->CCR[4] = speed;
}
void Motor_Left_Backward(uint16_t speed) {
if (speed > TIMER_A0_PWM_PERIOD_TICKS) speed = TIMER_A0_PWM_PERIOD_TICKS;
P5->OUT |= LEFT_DIR_PIN;
TIMER_A0->CCR[4] = speed;
}
void Motor_Right_Forward(uint16_t speed) {
if (speed > TIMER_A0_PWM_PERIOD_TICKS) speed = TIMER_A0_PWM_PERIOD_TICKS;
P5->OUT &= ~RIGHT_DIR_PIN;
TIMER_A0->CCR[3] = speed;
}
void Motor_Right_Backward(uint16_t speed) {
if (speed > TIMER_A0_PWM_PERIOD_TICKS) speed = TIMER_A0_PWM_PERIOD_TICKS;
P5->OUT |= RIGHT_DIR_PIN;
TIMER_A0->CCR[3] = speed;
}
void Motor_Left_Stop(void) {
TIMER_A0->CCR[4] = 0;
}
void Motor_Right_Stop(void) {
TIMER_A0->CCR[3] = 0;
}
void Motor_Stop_All(void) {
Motor_Left_Stop();
Motor_Right_Stop();
}
/*
IMPLEMENTATION RPM FUNC.
*/
void rpm_tachometer_init(void) {
capture_init_timer_A3();
Timer_A2_Stall_Init();
}
uint32_t get_left_rpm(void) {
uint32_t period;
__disable_irq();
period = g_left_pulse_period;
__enable_irq();
if (period == 0) return 0;
return RPM_MAGIC_NUMBER / period;
}
uint32_t get_right_rpm(void) {
uint32_t period;
__disable_irq();
period = g_right_pulse_period;
__enable_irq();
if (period == 0) return 0;
return RPM_MAGIC_NUMBER / period;
}
void reset_pulse_counts(void) {
__disable_irq();
g_left_pulse_count = 0;
g_right_pulse_count = 0;
__enable_irq();
}
uint32_t get_left_pulse_count(void) {
uint32_t count;
__disable_irq();
count = g_left_pulse_count;
__enable_irq();
return count;
}
uint32_t get_right_pulse_count(void) {
uint32_t count;
__disable_irq();
count = g_right_pulse_count;
__enable_irq();
return count;
}
static void Timer_A2_Stall_Init(void) {
TIMER_A2->CTL = TIMER_A_CTL_SSEL__SMCLK |
TIMER_A_CTL_ID__2 |
TIMER_A_CTL_MC__STOP;
TIMER_A2->CCTL[0] = TIMER_A_CCTLN_CCIE;
TIMER_A2->CCR[0] = (STALL_TIMER_PERIOD - 1);
TIMER_A2->EX0 = TIMER_A_EX0_TAIDEX_5;
NVIC->IP[3] = (NVIC->IP[3] & 0xFFFFFF00) | 0x40;
NVIC->ISER[0] = 1 << TA2_0_IRQn;
TIMER_A2->CTL |= TIMER_A_CTL_MC__UP | TIMER_A_CTL_CLR;
}
void TA2_0_IRQHandler(void) {
TIMER_A2->CCTL[0] &= ~TIMER_A_CCTLN_CCIFG;
if (g_left_new_data == 0) g_left_pulse_period = 0;
else
g_left_new_data = 0;
if (g_right_new_data == 0) g_right_pulse_period = 0;
else
g_right_new_data = 0;
}
static void capture_init_timer_A3(void) {
TIMER_A3->CTL = TIMER_A_CTL_SSEL__SMCLK |
TIMER_A_CTL_MC__CONTINUOUS |
TIMER_A_CTL_ID__1 |
TIMER_A_CTL_CLR;
P10->SEL0 |= BIT4;
P10->SEL1 &= ~BIT4;
P10->DIR &= ~BIT4;
TIMER_A3->CCTL[0] = TIMER_A_CCTLN_CM_1 | TIMER_A_CCTLN_CCIS_0 |
TIMER_A_CCTLN_SCS | TIMER_A_CCTLN_CAP | TIMER_A_CCTLN_CCIE;
P10->SEL0 |= BIT5;
P10->SEL1 &= ~BIT5;
P10->DIR &= ~BIT5;
TIMER_A3->CCTL[1] = TIMER_A_CCTLN_CM_1 | TIMER_A_CCTLN_CCIS_0 |
TIMER_A_CCTLN_SCS | TIMER_A_CCTLN_CAP | TIMER_A_CCTLN_CCIE;
NVIC->IP[3] = (NVIC->IP[3] & 0x00FFFFFF) | 0x40000000;
NVIC->ISER[0] = 1 << TA3_0_IRQn;
NVIC->IP[4] = (NVIC->IP[4] & 0xFFFFFF00) | 0x40;
NVIC->ISER[0] = 1 << TA3_N_IRQn;
}
void TA3_0_IRQHandler(void) {
TIMER_A3->CCTL[0] &= ~TIMER_A_CCTLN_CCIFG;
uint16_t current_capture = TIMER_A3->CCR[0];
uint32_t period = (current_capture > g_last_right_capture) ? (current_capture - g_last_right_capture) : ((0xFFFF - g_last_right_capture) + current_capture + 1);
g_right_pulse_period = period;
g_right_new_data = 1;
g_last_right_capture = current_capture;
g_right_pulse_count++;
}
void TA3_N_IRQHandler(void) {
if (TIMER_A3->CCTL[1] & TIMER_A_CCTLN_CCIFG) {
TIMER_A3->CCTL[1] &= ~TIMER_A_CCTLN_CCIFG;
uint16_t current_capture = TIMER_A3->CCR[1];
uint32_t period = (current_capture > g_last_left_capture) ? (current_capture - g_last_left_capture) : ((0xFFFF - g_last_left_capture) + current_capture + 1);
g_left_pulse_period = period;
g_left_new_data = 1;
g_last_left_capture = current_capture;
g_left_pulse_count++;
}
}

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/******************************************************************************
*
* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Default linker command file for Texas Instruments MSP432P401R
*
* File creation date: 12/06/17
*
*****************************************************************************/
/* Suppress warnings and errors: */
/* #10199-D CRC table operator (crc_table_for_<>) ignored:
CRC table operator cannot be associated with empty output section */
--diag_suppress=10199
--retain=flashMailbox
MEMORY
{
MAIN (RX) : origin = 0x00000000, length = 0x00040000
INFO (RX) : origin = 0x00200000, length = 0x00004000
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
ALIAS
{
SRAM_CODE (RWX): origin = 0x01000000
SRAM_DATA (RW) : origin = 0x20000000
} length = 0x00010000
#else
/* Hint: If the user wants to use ram functions, please observe that SRAM_CODE */
/* and SRAM_DATA memory areas are overlapping. You need to take measures to separate */
/* data from code in RAM. This is only valid for Compiler version earlier than 15.09.0.STS.*/
SRAM_CODE (RWX): origin = 0x01000000, length = 0x00010000
SRAM_DATA (RW) : origin = 0x20000000, length = 0x00010000
#endif
#endif
}
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* A heap size of 1024 bytes is recommended when you plan to use printf() */
/* for debug output to the console window. */
/* */
/* --heap_size=1024 */
/* --stack_size=512 */
/* --library=rtsv7M4_T_le_eabi.lib */
/* Section allocation in memory */
SECTIONS
{
#ifndef gen_crc_table
.intvecs: > 0x00000000
.text : > MAIN
.const : > MAIN
.cinit : > MAIN
.pinit : > MAIN
.init_array : > MAIN
.binit : {} > MAIN
/* The following sections show the usage of the INFO flash memory */
/* INFO flash memory is intended to be used for the following */
/* device specific purposes: */
/* Flash mailbox for device security operations */
.flashMailbox : > 0x00200000
/* TLV table for device identification and characterization */
.tlvTable : > 0x00201000
/* BSL area for device bootstrap loader */
.bslArea : > 0x00202000
#else
.intvecs: > 0x00000000, crc_table(crc_table_for_intvecs)
.text : > MAIN, crc_table(crc_table_for_text)
.const : > MAIN, crc_table(crc_table_for_const)
.cinit : > MAIN, crc_table(crc_table_for_cinit)
.pinit : > MAIN, crc_table(crc_table_for_pinit)
.init_array : > MAIN, crc_table(crc_table_for_init_array)
.binit : {} > MAIN, crc_table(crc_table_for_binit)
/* The following sections show the usage of the INFO flash memory */
/* INFO flash memory is intended to be used for the following */
/* device specific purposes: */
/* Flash mailbox for device security operations */
.flashMailbox : > 0x00200000, crc_table(crc_table_for_flashMailbox)
/* TLV table for device identification and characterization */
/* This one is read only memory in flash - generate no CRC */
.tlvTable : > 0x00201000
/* BSL area for device bootstrap loader */
.bslArea : > 0x00202000, crc_table(crc_table_for_bslArea)
.TI.crctab : > MAIN
#endif
.vtable : > 0x20000000
.data : > SRAM_DATA
.bss : > SRAM_DATA
.sysmem : > SRAM_DATA
.stack : > SRAM_DATA (HIGH)
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
.TI.ramfunc : {} load=MAIN, run=SRAM_CODE, table(BINIT)
#endif
#endif
}
/* Symbolic definition of the WDTCTL register for RTS */
WDTCTL_SYM = 0x4000480C;

206
labs/lab_w8/startup_msp432p401r_ccs.c Normal file
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/******************************************************************************
*
* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* MSP432P401R Interrupt Vector Table
*
*****************************************************************************/
#include <stdint.h>
/* Linker variable that marks the top of the stack. */
extern unsigned long __STACK_END;
/* External declaration for the reset handler that is to be called when the */
/* processor is started */
extern void _c_int00(void);
/* External declaration for system initialization function */
extern void SystemInit(void);
/* Forward declaration of the default fault handlers. */
void Default_Handler (void) __attribute__((weak));
extern void Reset_Handler (void) __attribute__((weak));
/* Cortex-M4 Processor Exceptions */
extern void NMI_Handler (void) __attribute__((weak, alias("Default_Handler")));
extern void HardFault_Handler (void) __attribute__((weak, alias("Default_Handler")));
extern void MemManage_Handler (void) __attribute__((weak, alias("Default_Handler")));
extern void BusFault_Handler (void) __attribute__((weak, alias("Default_Handler")));
extern void UsageFault_Handler (void) __attribute__((weak, alias("Default_Handler")));
extern void SVC_Handler (void) __attribute__((weak, alias("Default_Handler")));
extern void DebugMon_Handler (void) __attribute__((weak, alias("Default_Handler")));
extern void PendSV_Handler (void) __attribute__((weak, alias("Default_Handler")));
/* device specific interrupt handler */
extern void SysTick_Handler (void) __attribute__((weak,alias("Default_Handler")));
extern void PSS_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void CS_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void PCM_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void WDT_A_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void FPU_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void FLCTL_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void COMP_E0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void COMP_E1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA0_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA0_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA1_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA1_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA2_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA2_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA3_0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void TA3_N_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIA0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIA1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIA2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIA3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIB0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIB1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIB2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void EUSCIB3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void ADC14_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void T32_INT1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void T32_INT2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void T32_INTC_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void AES256_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void RTC_C_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void DMA_ERR_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void DMA_INT3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void DMA_INT2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void DMA_INT1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void DMA_INT0_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void PORT1_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void PORT2_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void PORT3_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void PORT4_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void PORT5_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
extern void PORT6_IRQHandler (void) __attribute__((weak,alias("Default_Handler")));
/* Interrupt vector table. Note that the proper constructs must be placed on this to */
/* ensure that it ends up at physical address 0x0000.0000 or at the start of */
/* the program if located at a start address other than 0. */
#pragma RETAIN(interruptVectors)
#pragma DATA_SECTION(interruptVectors, ".intvecs")
void (* const interruptVectors[])(void) =
{
(void (*)(void))((uint32_t)&__STACK_END),
/* The initial stack pointer */
Reset_Handler, /* The reset handler */
NMI_Handler, /* The NMI handler */
HardFault_Handler, /* The hard fault handler */
MemManage_Handler, /* The MPU fault handler */
BusFault_Handler, /* The bus fault handler */
UsageFault_Handler, /* The usage fault handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* SVCall handler */
DebugMon_Handler, /* Debug monitor handler */
0, /* Reserved */
PendSV_Handler, /* The PendSV handler */
SysTick_Handler, /* The SysTick handler */
PSS_IRQHandler, /* PSS Interrupt */
CS_IRQHandler, /* CS Interrupt */
PCM_IRQHandler, /* PCM Interrupt */
WDT_A_IRQHandler, /* WDT_A Interrupt */
FPU_IRQHandler, /* FPU Interrupt */
FLCTL_IRQHandler, /* Flash Controller Interrupt*/
COMP_E0_IRQHandler, /* COMP_E0 Interrupt */
COMP_E1_IRQHandler, /* COMP_E1 Interrupt */
TA0_0_IRQHandler, /* TA0_0 Interrupt */
TA0_N_IRQHandler, /* TA0_N Interrupt */
TA1_0_IRQHandler, /* TA1_0 Interrupt */
TA1_N_IRQHandler, /* TA1_N Interrupt */
TA2_0_IRQHandler, /* TA2_0 Interrupt */
TA2_N_IRQHandler, /* TA2_N Interrupt */
TA3_0_IRQHandler, /* TA3_0 Interrupt */
TA3_N_IRQHandler, /* TA3_N Interrupt */
EUSCIA0_IRQHandler, /* EUSCIA0 Interrupt */
EUSCIA1_IRQHandler, /* EUSCIA1 Interrupt */
EUSCIA2_IRQHandler, /* EUSCIA2 Interrupt */
EUSCIA3_IRQHandler, /* EUSCIA3 Interrupt */
EUSCIB0_IRQHandler, /* EUSCIB0 Interrupt */
EUSCIB1_IRQHandler, /* EUSCIB1 Interrupt */
EUSCIB2_IRQHandler, /* EUSCIB2 Interrupt */
EUSCIB3_IRQHandler, /* EUSCIB3 Interrupt */
ADC14_IRQHandler, /* ADC14 Interrupt */
T32_INT1_IRQHandler, /* T32_INT1 Interrupt */
T32_INT2_IRQHandler, /* T32_INT2 Interrupt */
T32_INTC_IRQHandler, /* T32_INTC Interrupt */
AES256_IRQHandler, /* AES256 Interrupt */
RTC_C_IRQHandler, /* RTC_C Interrupt */
DMA_ERR_IRQHandler, /* DMA_ERR Interrupt */
DMA_INT3_IRQHandler, /* DMA_INT3 Interrupt */
DMA_INT2_IRQHandler, /* DMA_INT2 Interrupt */
DMA_INT1_IRQHandler, /* DMA_INT1 Interrupt */
DMA_INT0_IRQHandler, /* DMA_INT0 Interrupt */
PORT1_IRQHandler, /* Port1 Interrupt */
PORT2_IRQHandler, /* Port2 Interrupt */
PORT3_IRQHandler, /* Port3 Interrupt */
PORT4_IRQHandler, /* Port4 Interrupt */
PORT5_IRQHandler, /* Port5 Interrupt */
PORT6_IRQHandler /* Port6 Interrupt */
};
/* Forward declaration of the default fault handlers. */
/* This is the code that gets called when the processor first starts execution */
/* following a reset event. Only the absolutely necessary set is performed, */
/* after which the application supplied entry() routine is called. Any fancy */
/* actions (such as making decisions based on the reset cause register, and */
/* resetting the bits in that register) are left solely in the hands of the */
/* application. */
void Reset_Handler(void)
{
SystemInit();
/* Jump to the CCS C Initialization Routine. */
__asm(" .global _c_int00\n"
" b.w _c_int00");
}
/* This is the code that gets called when the processor receives an unexpected */
/* interrupt. This simply enters an infinite loop, preserving the system state */
/* for examination by a debugger. */
void Default_Handler(void)
{
/* Fault trap exempt from ULP advisor */
#pragma diag_push
#pragma CHECK_ULP("-2.1")
/* Enter an infinite loop. */
while(1)
{
}
#pragma diag_pop
}

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/******************************************************************************
* @file system_msp432p401r.c
* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for
* MSP432P401R
* @version 3.231
* @date 01/26/18
*
* @note View configuration instructions embedded in comments
*
******************************************************************************/
//*****************************************************************************
//
// Copyright (C) 2015 - 2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#include <stdint.h>
#include "msp.h"
/*--------------------- Configuration Instructions ----------------------------
1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1:
#define __HALT_WDT 1
2. Insert your desired CPU frequency in Hz at:
#define __SYSTEM_CLOCK 12000000
3. If you prefer the DC-DC power regulator (more efficient at higher
frequencies), set the __REGULATOR to 1:
#define __REGULATOR 1
*---------------------------------------------------------------------------*/
/*--------------------- Watchdog Timer Configuration ------------------------*/
// Halt the Watchdog Timer
// <0> Do not halt the WDT
// <1> Halt the WDT
#define __HALT_WDT 1
/*--------------------- CPU Frequency Configuration -------------------------*/
// CPU Frequency
// <1500000> 1.5 MHz
// <3000000> 3 MHz
// <12000000> 12 MHz
// <24000000> 24 MHz
// <48000000> 48 MHz
#define __SYSTEM_CLOCK 3000000
/*--------------------- Power Regulator Configuration -----------------------*/
// Power Regulator Mode
// <0> LDO
// <1> DC-DC
#define __REGULATOR 0
/*----------------------------------------------------------------------------
Define clocks, used for SystemCoreClockUpdate()
*---------------------------------------------------------------------------*/
#define __VLOCLK 10000
#define __MODCLK 24000000
#define __LFXT 32768
#define __HFXT 48000000
/*----------------------------------------------------------------------------
Clock Variable definitions
*---------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
uint32_t source = 0, divider = 0, dividerValue = 0, centeredFreq = 0, calVal = 0;
int16_t dcoTune = 0;
float dcoConst = 0.0;
divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS;
dividerValue = 1 << divider;
source = CS->CTL1 & CS_CTL1_SELM_MASK;
switch(source)
{
case CS_CTL1_SELM__LFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
}
else
{
SystemCoreClock = __LFXT / dividerValue;
}
break;
case CS_CTL1_SELM__VLOCLK:
SystemCoreClock = __VLOCLK / dividerValue;
break;
case CS_CTL1_SELM__REFOCLK:
if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
break;
case CS_CTL1_SELM__DCOCLK:
dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS;
switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK)
{
case CS_CTL0_DCORSEL_0:
centeredFreq = 1500000;
break;
case CS_CTL0_DCORSEL_1:
centeredFreq = 3000000;
break;
case CS_CTL0_DCORSEL_2:
centeredFreq = 6000000;
break;
case CS_CTL0_DCORSEL_3:
centeredFreq = 12000000;
break;
case CS_CTL0_DCORSEL_4:
centeredFreq = 24000000;
break;
case CS_CTL0_DCORSEL_5:
centeredFreq = 48000000;
break;
}
if(dcoTune == 0)
{
SystemCoreClock = centeredFreq;
}
else
{
if(dcoTune & 0x1000)
{
dcoTune = dcoTune | 0xF000;
}
if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS))
{
dcoConst = *((volatile const float *) &TLV->DCOER_CONSTK_RSEL04);
calVal = TLV->DCOER_FCAL_RSEL04;
}
/* Internal Resistor */
else
{
dcoConst = *((volatile const float *) &TLV->DCOIR_CONSTK_RSEL04);
calVal = TLV->DCOIR_FCAL_RSEL04;
}
SystemCoreClock = (uint32_t) ((centeredFreq)
/ (1
- ((dcoConst * dcoTune)
/ (8 * (1 + dcoConst * (768 - calVal))))));
}
break;
case CS_CTL1_SELM__MODOSC:
SystemCoreClock = __MODCLK / dividerValue;
break;
case CS_CTL1_SELM__HFXTCLK:
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
// Clear interrupt flag
CS->KEY = CS_KEY_VAL;
CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
CS->KEY = 1;
if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS))
{
if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS))
{
SystemCoreClock = (128000 / dividerValue);
}
else
{
SystemCoreClock = (32000 / dividerValue);
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
}
else
{
SystemCoreClock = __HFXT / dividerValue;
}
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*
* Performs the following initialization steps:
* 1. Enables the FPU
* 2. Halts the WDT if requested
* 3. Enables all SRAM banks
* 4. Sets up power regulator and VCORE
* 5. Enable Flash wait states if needed
* 6. Change MCLK to desired frequency
* 7. Enable Flash read buffering
*/
void SystemInit(void)
{
// Enable FPU if used
#if (__FPU_USED == 1) // __FPU_USED is defined in core_cm4.h
SCB->CPACR |= ((3UL << 10 * 2) | // Set CP10 Full Access
(3UL << 11 * 2)); // Set CP11 Full Access
#endif
#if (__HALT_WDT == 1)
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT
#endif
SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks
#if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 1.5 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 3000000) // 3 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
#endif
// No flash wait states necessary
// DCO = 3 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 12000000) // 12 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// No flash wait states necessary
// DCO = 12 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 24000000) // 24 MHz
// Default VCORE is LDO VCORE0 so no change necessary
// Switches LDO VCORE0 to DCDC VCORE0 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 1 flash wait state (BANK0 VCORE0 max is 12 MHz)
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
// DCO = 24 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#elif (__SYSTEM_CLOCK == 48000000) // 48 MHz
// Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
// Switches LDO VCORE1 to DCDC VCORE1 if requested
#if __REGULATOR
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5;
while((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
#endif
// 1 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz)
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1;
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1;
// DCO = 48 MHz; MCLK = source
CS->KEY = CS_KEY_VAL; // Unlock CS module for register access
CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz
CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK;
// Select MCLK as DCO source
CS->KEY = 0;
// Set Flash Bank read buffering
FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI);
FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI);
#endif
}

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="configuration_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe">
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<property Type="choicelist" Value="2" id="The JTAG TCLK Frequency (MHz)">
<choice Name="Fixed with user selected faster value" value="SPECIFIC">
<property Type="choicelist" Value="2" id="Select TCK Setting"/>
</choice>
</property>
<property Type="choicelist" Value="2" id="SWD Mode Settings">
<choice Name="SWD Mode - Aux COM port is target TDO pin" value="nothing"/>
</property>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="MSP432P401R" href="devices/msp432p401r.xml" id="MSP432P401R" xml="msp432p401r.xml" xmlpath="devices"/>
</platform>
</connection>
</configuration>
</configurations>

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The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
on the device and connection settings specified in your project on the Properties > General page.
Please note that in automatic target-configuration management, changes to the project's device and/or
connection settings will either modify an existing or generate a new target-configuration file. Thus,
if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
you may create your own target-configuration file for this project and manage it manually. You can
always switch back to automatic target-configuration management by checking the "Manage the project's
target-configuration automatically" checkbox on the project's Properties > General page.

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